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From: [e-mail] (Ola Lidholm)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Zorro (Dave Haynie Please?)
Date: 10 Mar 1996 21:11:53 GMT
Organization: Uniplus Internet Access
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>> I am currently writing a series of articles about the Zorro busses in one
>> of the new swedish Amiga Magazines: "Svenska Amiga Magasin".
>>
>> I have a question about the "DOE" signal in the bus, in "A500/A2000
>> technical reference manual" it says that this signal is ment to be used to
>> enable the buffers on the expansionsion board (PIC), and also it says that
>> the timing on this signal changes if the buscycle is a read or write cycle.
>> The "RKRM: Hardware" does not give me any more clues either.
>>
>> So what I'm wondering is, are there any timing diagrams available where you
>> can see exactly how the timg changes, or an exaple as to how you actually
>> should use this signal. In the "PIC example" also published in the above
>> mentioned book, the signal isn't used at all; it is simply stated that that
>> pin (#93) is "reserved".

 DE> ---What DOE is---

 DE> The A500/A2000 Technical Reference manual has some PAL equations for
 DE> the bus logic, try page 232, /DBOE equation.
 DE> There's a couple of typos (/D5 should be /DS, and the comments in the
 DE> /DBOE equation about 'reads' should say 'writes' and vice versa).
 DE> (BTW, the TESTRAM PIC PAL equation section also is riddled with typos,
 DE> in DBOE, SHUTUP should be /SHUTUP, in PRECON, /AD should be /A4,
 DE> and in CONOUT, ASQ should be /ASQ.)

OK, thanks for the info on the errors in the manual, that was really helpful.
Altough I already figured all but the CONOUT error out by myself... :)

 DE> While these seem to be for the A2000 (the early German model), I
 DE> assume that the equations are functionally the same for the B2000.

Well, they have to be compatible anyway I guess, anyway :)

 DE> Essentially, DOE gets asserted when AS does on writes,
 DE> and on reads, gets asserted when DS and the delayed AS does.
 DE> The equations should put this into more detail.

Ah... OK, I'm a bit confused here though, looking at the A2000 schematics,
this PAL's output "DBOE" is _not_ connected to the Zorro bus DOE, but to the
backplanes buffers. DOE on the zorro bus is simply the compliment of the "ASQ"
input to the above mentioned PAL.

So, I am getting more and more convinced that the timing on this "DOE" signal
that actually _is_ available in the Zorro bus, does not at all change it's
timing when doing read or write buscycles. There must simply be some typo,
or misconcenption between the DOE and DBOE signal in the A500/A2000 tech ref man?

Correct me if I am wrong here...

 DE> Thus, on a write, DOE gets asserted immediately, since the bus doesn't
 DE> have to switch directions.

If we are talking about DBOE and not DOE I agree with you :)

 DE> On a read, DOE only gets asserted when the delayed address strobe
 DE> ASQ does, which, from what I understand, is the next 7 MHz cycle
 DE> after AS gets asserted.  Thus, this delay gives the CPU time to
 DE> switch its bus directions around before your PIC starts to output
 DE> its data onto the bus.

OK, basically, anyway as I understand it, DOE has the same timing as the
/AS_DELAYED singal on the PIC example.

Again, correct me if I am wrong.

 DE> You can invert this and use it to control the /OE line on your data
 DE> bus buffers to prevent the CPU and the PIC from both attempting to
 DE> drive the bus during a read if your AutoConfig logic doesn't
 DE> already do this.

 DE> ---PIC example comments---

 DE> The PIC example creates the equivalent of DOE in U9.1
 DE> (actually its complement) - the unconnected /Q output
 DE> is functionally equivalent to DOE.  You could use DOE instead
 DE> of AS_DELAYED*, and change the U3 PAL equations (invert that input
 DE> line, which is /ASQ in the equation)
 DE> thus eliminating U9.1 entirely.
 DE> Of course, in this example, another delay element is specified
 DE> for the SRAM, so you don't really save anything by eliminating
 DE> U9.1.

Yes, this was basically the reason behind my question, I wanted to
eleminate U9, but found no real good dox on DOE.

So anyway, back to the drawing board :)

 DE> For that matter, U4.1 and U4.2 could be eliminated, as the output
 DE> of U4.2 is the 7M signal.

Yes, figured that out to.

 DE> This part of the circuit seems to mainly be here for compatibility
 DE> with the A500 side expansion port, since it does not have DOE or 7M.
 DE> If you'll notice carefully, this is what is required on the
 DE> A500 to Zorro II hacks.

Hmm. Ah, yes, you are probably right about that, the design is somewhat
aimed as to work both in A500 and A2000.
That would explain some of the pecurialities (or how ever that word is
spelled :).

 DE> ---

>> I have also heard about a Zorro-III example design "BigRam", that was
>> available to developers before commodore whent bancrupt. Is this anything
>> that would be available for the public, or do you have to be a registered
>> developer?

 DE> The only place that I know of where this was published was the
 DE> Devcon '91 notes.  Developers had to sign nasty non-disclosure
 DE> agreements to get these, and I havn't heard of these becoming
 DE> public, so I doubt you'd be able to legitimately get a copy of
 DE> these without being a developer.

OK, well, anyway, this is for AT to answer...

Thanks, you helped a lot.

---
 Ola Lidholm
 [e-mail]
 [e-mail]
 ola lidholm@2:204/204.25
 http://www.plea.se/~olal